Ramune Nagisetty is a Senior Principal Engineer and Director of Process and Product Integration in Intel’s Technology Development group. In 2006, she became the Director of Strategic Technology Programs in Intel Labs.
Ramune went on to lead research in systems engineering and prototyping. She has championed the use of chiplets and package level integration to reduce portfolio cost, scale innovation, and speed time to market. Her vision for a future industry-scale chiplet ecosystem has been featured in Wired Magazine, AnandTech, and IEEE Spectrum.
Nagisetty earned an MSEE specializing in solid-state physics from UC Berkeley and joined Intel in 1995. She delivered Intel’s first strained silicon technology, led the transition to 300 mm wafers, and did pathfinding for Hi-K metal gate and FinFET transistors.